This invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and more particularly to a semiconductor integrated injection logic circuit device and a method of manufacturing the same.
The integrated injection logic circuit (hereinafter referred to as the I.sup.2 L circuit) is of a simple structure totally different from the conventional bipolar logic circuit, and such I.sup.2 L circuit conception is described in, for instance, Nikkei Electronics, May 6, 1974, pp. 85-90, and U.S. Pat. Nos. 3,736,477 and 3,816,758. The basic arrangement of the gate circuit thereof is shown in FIG. 3a and its structural diagram is shown in FIG. 3b. The most salient feature of this circuit is that there are used a complementary pair of transistors. An NPN transistor Q1 of the multicollector type is disposed vertically in the substrate to act as an inverter, while a lateral PNP transistor Q2 acts as a constant current source to feed current to the collector of the NPN transistor of the previous stage (not shown) connected to a base 52 of the NPN transistor Q1 or to an input terminal B. This lateral PNP transistor also functions as a collector load of the NPN transistor of the preceding stage. An emitter 51 of this lateral PNP transistor is generally called an injector because it feeds current.
Such a gate circuit, as shown in FIG. 3b, can be constituted only from transistors without using any resistance for both the power source and the load. That is, an n.sup.+ substrate 1 forms the common emitter En of the gate transistor Q1 and island-like n.sup.+ layers 61, 62, 63 are arranged spaced apart from each other close to the surface to form multicollectors C1-C3. Thus, this circuit is characterized in that the NPN transistors are constituted from inverted transistors where the substrate 1 is designed to act as an emitter.